The present invention relates to the field of buckling beam probe apparatus. More specifically, the present invention relates to space transformers for buckling beam probe apparatus.
Chips are becoming more and more compact and perform an increasing number of logical operations at higher and higher clocking frequencies. For testing purposes, chips typically provide a two dimensional array of contacting pads, which can be accessed, e.g. by buckling beam probe apparatus as it is well-known to those skilled in the art. High performance chips have a larger number of contacting pads with smaller size and smaller pitch. Due to the high contact densities on the chip top surface pad arrays are being more and more frequently replaced by ball grid arrays.
Buckling beam probe apparatus are typically utilized to test high performance chips. Their design concept is mainly based on a number of buckling beam probes that are held in a parallel fashion such that they can provide uniform access to contact pad arrays and/or ball grid arrays. To provide uniform contacting characteristics, e.g. equal contact force, scrub length etc., it is crucial that the buckling beams have identical configurations and are embedded and accessed within the probe apparatus under uniform conditions. Hence, the access side of the buckling beam matrix has an essentially identical geometric configuration to the contacting side. At the access side a space transformer provides electrical contact with each individual buckling beam. Consequently, the space transformer has to provide the same density of contacts for the buckling beams as it is dictated by the pads on the chip to be tested.
Unfortunately, the contact between the buckling beams and the space transformer is under higher cyclic strain than the contacts of the chip. The contact pads or contacting balls on the chip are only exposed to the loads and abrasion during the testing sequence once. Then the die chips are cut and packaged. The contact pads of the space transformer are exposed to repeated loading during each test cycle and subjected to increased wear.
Due to increased voltages and currents applied to the chip during the test, the contacts of the space transformer additionally have to endure higher electrical strains than the chip contacts during their regular use.
The discrepancies between the mechanical and electrical strain of space transformer contacts and chip contacts become more pronounced, the more the geometrical configuration of the contact pads or contact balls of the chips are pushed to the limits defined by the regular use of the chip.
The functional testing of the chips on the wafer level becomes an increasingly critical step in the fabrication process of high performance chips. The complexity of the logical operations that need to be tested make the testing sequence more time consuming. In addition, the chips have to be tested under elevated temperatures, which introduces a time consuming step in the chip fabrication. Therefore, it becomes desirable to test more and more chips simultaneously on the wafer level.
The space transformer not only provides contact with the buckling beams but also has to provide a conductive path between the tightly arrayed buckling beams and peripheral contact pads where relatively bulky cables are attached. For high speed testing at high clocking frequencies, where the parasitic inductive and capacitate limitations of the conductive path become relevant, the space transformer also provides intermediate logical circuitry. This intermediate logical circuitry works to up/down convert testing signal frequencies from low transmission frequencies to high testing frequencies. The low transmission frequencies are typically at levels where the inductance and capacitance in the transmission path is irrelevant.
The frequency converting circuitry is ideally placed within the space transformer in close proximity to the buckling beams to reduce the inductive path to the chip as much as possible. Frequency down converting of electric signals may be accomplished by dividing them and assigning them to a higher number of conductive paths. In summary, the space transformer provides a spatial expansion of a constant and/or increasing number of conductive paths in direction from the tightly arrayed buckling beams to the large peripheral contacts.
A number of space transformer systems have been developed to keep up with the ever increasing demands as described above. Specifically, more intermediate structures fabricated with independent technologies are being combined to bridge the scale differences between the central buckling beam contact density and the peripheral contact density.
U.S. Pat. No. 5,132,613, for instance, describes a low inductance side mount decoupling test structure that utilizes a stacked substrate MLC space transformer. The space transformer consists of an interface substrate, a xe2x80x9cpersonalxe2x80x9d substrate and an interposer block. It is fabricated from a number of individual layers that are laminated and sintered together.
Even though the described test structure provides a good scaling ratio between the central probes and the peripheral contacts, the fabrication process is time consuming and complicated. The invention does not take into consideration specific needs for contacting the probes.
U.S. Pat. No. 5,806,181 describes xe2x80x9ccontact carriers for populating larger substrates with spring contactsxe2x80x9d. The scaling of the central probe contacts and the peripheral contacts is provided by a number of stages that are connected to each other by wire bonding. The wire bonding introduces additional inductance and affects the performance of the probe apparatus at high frequencies. The probes themselves are also wire bonded to the space transformer.
U.S. Pat. No. 5,821,763 describes a test probe for high density integrated circuits, methods of fabrication and use thereof. A ceramic packaging substrate used to package integrated circuit chips is utilized as a space transformer. The invention provides the space transformer by utilizing a structure developed for packaging of integrated circuit chips. The probes are wire bonded to the space transformer, which is optionally connected to a second fan-out structure by an interposer. The invention is also subject to the limitations described for the above patents.
It has become common practice to utilize packaging structures of circuit chips as space transformers. Since the packaging provides a similar fanning-out of the conductive paths between the circuit chip and the printed circuit board, it is preferably utilized as a space transformer. Never the less, specifics of the packaging impose limitations in its feasibility for space transformer.
First, for testing a circuit chip different signal and voltage schemes have to be applied. This increases the number of required conductive paths. Since package systems for chips are typically mass-produced, these slight differences can be compensated only with a more than proportional effort and expense.
Second, package systems are primarily designed for a permanent connection to circuit chips rather than for a high number of contacting actions. As a result, the preferred method of contacting beam probes to space transformers adapted from packaging structures is wire bonding. Wire bonding becomes increasingly disadvantageous for conductively connecting beam probes to the space transformer at high frequencies as it is described in the above.
Third, package systems are typically designed for a single circuit chip. In a test probe apparatus that tests a number of circuit chips simultaneously space transformers based on packaging structures have limited use since different fan-out concepts for the conductive paths have to be utilized.
U.S. Pat. No. 4,038,599 discloses a high density wafer contacting and test system that utilizes a space transformer essentially made from silicon like a circuit chip. The space transformer has traces and logical circuitry to compose test signals from two orthogonal oriented trace arrays that traverse the space transformer. In that way, a low number of traces is utilized to provide a high number of probe beams with testing signals. The space transformer is a monolithic unit that provides the peripheral contact pads for the supply cables. The space transformer further provides contact pads against which ball-like heads of the probe beams are pressed.
The use of chip fabrication techniques to provide the space transformer is rooted in the need to include logical circuitry that is necessary to provide the large number of testing signals from a small number of conductive traces. The contact pads that are provided to the space transformer are subject to increased wear from repeated mechanical impact of the ball heads against the pads and potential oxidation in the contacting gap.
It is a primary object of the present invention to provide a space transformer that includes a primary structure that provides the contact to a high density beam probe matrix and provides an up scaled conductive connection between the beam probe matrix and a secondary space transformer structure.
It is another object of the present invention to provide the primary structure in a configuration that can be fabricated with techniques commonly utilized for the fabrication of circuit chips.
It is also an object of the present invention, to provide the primary structure with contacting features that allow to contact the individual probes of a high density beam probe matrix in a way that exceeds the geometric conditions defined by contact pad arrays and/or ball grid arrays of high performance circuit chips.
Finally, it is an object of the present invention to provide a method for mechanically and conductively combining the primary structure with other structures of the space transformer.
The present invention introduces a primary space transformer structure manufactured from silicon or other material used for the fabrication of circuit chips. In the preferred embodiment, the primary structure has vias such that the beam probes can be held by friction in the space transformer without having to impose an external contacting force on the primary structure. The primary structure has layers of metallized traces that allow to redistribute and fan out the conductive paths towards a intermediate connector system. The intermediate connector system provides the conductive connection between the primary structure and the beam probes. An adjacent secondary structure is provided and designed for contact with the intermediate connector system. The adjacent secondary structure serves to further scale up the spatial dimension between the individual contacts.
In the preferred embodiment, the intermediate connector system is a ball grid array, which may be located on the opposite side or the same side of the primary structure as the beam probes. The contact balls of the ball grid array contact pads of the secondary structure that fans out the conductive paths such that a printed circuit board may be contacted at a scale feasible for the printed circuit board.
The primary structure consists of a substrate that preferably contains the conductive traces and a ceramic structure that leads the primary structure the necessary stiffness. The substrate is bonded to the ceramic structure. In the case, where the ball grid array is on the opposite side of the beam probes, the ceramic structure has recesses where the contact balls are positioned.
In the preferred embodiment, the primary structure is pressed with the ball grid array against the contact pads of the secondary structure by suitable elements like, for instance, screws. In a following step the hollow space between primary and secondary structure is filled with a resin, which is cured in a final step.
In an alternate embodiment, the primary structure is conductively connected to the secondary structure via wire bonding performed on the periphery of the beam probe side of the primary structure. Adjustment screws allow to tune the position, orientation and/or eventually the planarity of the primary structure before it is fixated and bonded together with the secondary structure as it is described in the paragraph above.
The introduction of the primary structure allows, on the one hand, for more flexibility in the design of test probe apparatus because of the relatively easy fabrication of chip like structures. On the other hand, the selection of a primary structure that corresponds in its fabrication to that of circuit chips ensures the ability to keep pace with further down scaling in chip fabrication.